1. Field of the Invention
The present invention relates to digital computers and, more particularly, to a single-chip microcomputer.
The invention is best applicable to the provision of high-efficiency multiprocessor computing systems with a common memory field.
The invention is also applicable to process control systems and NC machine tools.
2. Description of the Prior Art
There is known a computer (cf. U.S. Pat. No. 3,710,324) comprising a processor, a memory and at least one peripheral unit having a means to generate a request in case of readiness. All these units are interconnected by a common bus. Combining such computers into a multiprocessor system is impossible without additional units. A combined system is poorly coupled and displays an improved efficiency only in solving a combination of problems, but not in solving an individual problem.
Single-chip microcomputers constructed as large scale integrated circuits have a number of important advantages. They are small in size, highly reliable and have a low power input; they are also cheap and versatile. At the same time the capacity of such microcomputers is insufficient for solving a number of problems. This necessitates combining single-chip microcomputers into a high-capacity multiprocessor computing system. In order to make such a system efficient in solving not only a combination of problems, but also individual problems, it is necessary that the system be provided with a common memory field accessible to all the processors it contains. It is also necessary that the capacity of the system increase in proportion to the amount of hardware.
From the technical standpoint, the closest prototype of the present invention is a single-chip microcomputer (cf. MCS-48. Microcomputer User's Manual, 1976, by Intel Corporation, 3065 Bowers Avenue, Santa Clara, Calif. 95051) comprising a computation process control unit and an operation execution unit. The computation process control unit is intended to decode instructions and form sequences of microinstructions to control microprocessor units. The microcomputer further incorporates a memory unit, an interface to connect the microcomputer to peripheral devices, a buffer storage cell, and a unit to control exchange of information transmitted through a system line. All the above units are interconnected by a bidirectional bus. The unit to control exchange of information transmitted through the system line forms signals to control the buffer storage cell and coordinates the order of exchange of information transmitted through the bidirectional bus and the system line.
A first output of the unit to control exchange of information transmitted through the system line is connected to a control input of the buffer storage cell. An input/output of the buffer storage cell, a first input/output of the unit to control exchange of information transmitted through the system line, and an input/output of the interface are a first input/output, a second input/output and a third input/output, respectively, of the single-chip microcomputer.
The memory unit of the single-chip microcomputer under review comprises a random-access memory and a read-only memory. The processor of the single-chip microcomputer comprises a program counter whose output is connected to an input of the interface and to an input of the read-only memory.
It is impossible to combine several single-chip microcomputers of this type into a multiprocessor system with a common memory field. The functional potentialities of such a microcomputer can be expanded through the use of more memory units, but this makes it harder to integrate single-chip microcomputers into a multiprocessor system and calls for additional peripheral equipment.